The present invention relates generally to a method of fabricating a semiconductor memory device, more particularly relates to a method of fabricating a semiconductor memory device for preventing phenomenon that shape of gate patterns of a memory cell is deformed while an impurity injection area is formed.
A semiconductor memory device includes a plurality of impurity injection areas which are injected with impurities. The impurity injection area may be injected with impurities of different concentration or different kind in accordance with electrical characteristics which the impurity injection area would have. Also, the depth of impurity injection area may be adjusted. The impurity injection areas having different characteristics from each other are formed by performing repeatedly a process of forming an impurity injection mask for opening only the impurity injection areas having the same characteristics and covering the other impurity injection areas, a process of injecting corresponding impurities into only the opened impurity injection areas through open area of the impurity injection mask, a process of removing the impurity injection mask and a cleaning process.
With high integration of the semiconductor memory device, widths of gate patterns of memory cells decrease and a space between gate patterns of the memory cells becomes narrow. However, processes for forming the impurity injection areas, including the process of removing the impurity injection mask and the cleaning process, are generally performed after forming the gate patterns of the semiconductor memory device. Therefore, a leaning phenomenon or a bending phenomenon of the gate patterns may occur. Hereinafter, the leaning phenomenon or the bending phenomenon of the gate pattern of the memory cell in semiconductor memory device, e.g. NAND flash memory device due to the process of forming the impurity injection area will be described in detail.
The NAND flash memory device includes a cell area in which memory cells for storing data are formed, a select transistor area in which a drain select transistor or a source select transistor for selecting the memory cells is formed, and a peripheral area in which driving/controlling transistors for driving/controlling the NAND flash memory device are formed. The memory cells in a cell string of the NAND flash memory device are connected in series between the source select transistor and the drain select transistor. A first impurity injection area which is a cell junction area is formed at both sides of a gate of memory cell (hereinafter, referred to as “cell gate”) in a semiconductor substrate of the cell area. A second impurity injection area which is a drain area or a source area is formed between gates of adjacent select transistors (hereinafter, referred to as “drain select gate”) in the semiconductor substrate of the select transistor region. A third impurity injection area which is a source area or a drain area is formed at both sides of a gate of a driving/controlling transistor (hereinafter, referred to as “driving gate”) in the semiconductor substrate of the peripheral area.
The first to the third impurity injection areas are formed after gate patterns including the cell gates, the source and the drain select gates and the driving gates are formed. The cell gate may have an aspect ratio higher than the source and the drain select transistors and the driving gate, and the space between the cell gates is narrower than the space between the source select gates, the space between the drain select gates and the space between the driving gates. Accordingly, the gate pattern is deformed mainly in the cell gate due to a process of forming the first to the third impurity injection areas.
Deformation of the cell gate may occur during the process of forming the second and the third impurity injection areas. The second and the third impurity injection areas may be formed with different concentration from the first impurity injection area or be formed by injecting impurities different from impurities in the first impurity injection area. Accordingly, to form the second impurity injection area or the third impurity injection area, the cell area is covered with an impurity injection mask for opening the peripheral area or the select transistor area, and then a process of injecting the impurities is performed. The impurity injection mask is removed through a strip process after the impurity injection process for forming the second impurity injection area or the third impurity injection area is performed, and a cleaning process is performed. Here, the cell gates which are formed with a narrow interval and a high aspect ratio may be deformed due to the process of removing the impurity injection mask for forming the second or the third impurity injection area and the cleaning process.